1. Field of the Invention
The present invention relates to a semiconductor device including a semiconductor memory circuit and, more particularly, to a mode switching circuit which permits easy switching between a normal operation mode and a test mode without an erroneous operation.
2. Description of the Related Art
The following describes a mode switching circuit of a semiconductor device equipped with a conventional semiconductor memory circuit. FIG. 3 is a circuit diagram illustrating a conventional mode switching circuit.
The conventional mode switching circuit includes an input terminal 501, an internal circuit 502, P-type MOS transistors 503 and 504, an N-type MOS transistor 505, and a voltage determination circuit 507.
The internal circuit 502 is connected with the input terminal 501 through a resistor 506. The internal circuit 502 is provided with an inverter for input signals, and a power supply voltage Vcc (e.g., 5V) is supplied thereto. The voltage determination circuit 507 is connected to a node N1. The P-type MOS transistors 503 and 504 are diode-connected between the input terminal 501 and a supply terminal such that they face in the opposite directions. The N-type MOS transistor 505 is diode-connected between the input terminal 501 and an earth terminal. The voltage determination circuit 507 has a voltage detection inverter for detecting the voltage of the input terminal 501 and a conversion inverter which carries out the level conversion of a detection signal to a power supply voltage Vcc. In the voltage detection inverter, the voltage of the node N1 is input to the power source thereof, while the power supply voltage Vcc is supplied to the input terminal thereof. In the conversion inverter, the power supply voltage Vcc is input to the power source thereof, while an output signal of the voltage detection inverter is supplied to the input terminal thereof. The voltage determination circuit 507 outputs a detection signal to the internal circuit 502.
The conventional mode switching circuit operates as described below to switch from a normal operation mode to a test mode (refer to, for example, patent document 1).
When a signal of a voltage (e.g., 0V to 5V) for the normal operation is supplied to the input terminal 501, a P-type MOS transistor 508 of the voltage determination circuit 507 turns off, because the source voltage changes in the range from 0V to 5V, and an N-type MOS transistor 509 turns on. This causes the voltage determination circuit 507 to output a Hi signal to the internal circuit 502, so that the internal circuit 502 maintains the normal operation mode.
Next, if a voltage (e.g., 10V) that is higher than the voltage for the normal operation is supplied to the input terminal 501, then the P-type MOS transistor 508 of the voltage determination circuit 507 turns on, because the source voltage rises to 10V, and the N-type MOS transistor 509 turns off. Hence, the voltage determination circuit 507 outputs a Lo signal to the internal circuit 502, causing the internal circuit 502 to switch to the test mode.    [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-269428
However, according to the prior art, a high voltage is applied to the input terminal used for the normal operation mode, so that it is necessary to provide a protection transistor to protect the input terminal and the internal circuit from the high voltage. It is also necessary to provide a voltage determination circuit to determine that the high voltage has been applied to the input terminal. This has been posing a problem of an increased area of the mode switching circuit.
In addition, the high voltage for engaging the test mode has to be set at a sufficiently higher level than that of the input voltage for the normal operation mode so as to prevent the test mode from being accidentally engaged. There has been, however, a problem in that securing an adequate margin to accommodate variations in the voltage determination circuit is difficult due to deteriorated withstand voltage of a protection transistor with the increasing trend toward miniaturization of the elements in a semiconductor integrated circuit and faster element operations.